Peripheral component interconnect PCI Express (or “PCIe”) is a high performance, generic and scalable system interconnect bus for a wide variety of applications ranging from personal computers to embedded applications. PCIe implements a serial, full duplex, multi-lane, point-to-point interconnect, packet-based, and switch based technology. Current versions of PCIe buses allow for a transfer rate of 2.5 Gb/Sec per lane, with a total of 32 lanes.
FIG. 1 shows an illustration of a typical architecture 100 of a computing device that includes a PCIe fabric. A host bridge 110 is coupled to endpoints 120, a CPU 130, a memory 140, and a switch 150. The peripheral components are connected through endpoints 120-1 to 120-N (120). Multiple point-to-point connections are accomplished by the switch 150, which provides the fanout for the I/O bus. The switch 150 provides peer-to-peer communication between different endpoints 120. That is, traffic between the switch 150 and endpoints 120 that does not involve cache-coherent memory transfers, is not forwarded to the host bridge 110. The switch 150 is shown as a separate logical element but it could be integrated into the host bridge 110.
As depicted in FIG. 2 the PCIe is a layered protocol bus, consisting of a transaction layer 210, a data link layer 220, and a physical layer 230. The PCIe implements split transactions, i.e., transactions with request and response separated by time, allowing the link to carry other traffic while the target device gathers data for the response. With this aim, the primary function of the transaction layer 210 is to assemble and disassemble transaction layer packets (TLPs). TLPs are used to carry transactions, where each TLP has a unique identifier that enables a response directed at the originator. The data link layer 220 acts as an intermediate between the transaction layer 210 and the physical layer 230 and provides a reliable mechanism for exchanging TLPs. The data link layer 220 implements error checking (known as “LCRC”) and retransmission mechanisms. LCRC and sequencing are applied on received TLPs and if an error is detected, a data link retry is activated. The physical layer 230 consists of an electrical sub-layer 234 and logical sub-layer 232. The sub-layer 232 is a transmitter and receiver pair implementing symbol mapping, serialization and de-serialization of data. At the electrical sub-layer 234, each lane utilizes two unidirectional low-voltage differential signaling (LVDS) pairs at 2.5 Gbit/s or 5 Gbit/s for transmit and receive symbols from the logical sub-block 232.
In the current technology, peripheral components are physically coupled to the PCIe. To wirelessly connect the peripheral devices a new protocol has to be defined. For example, the UWB is a wireless technology for USB, and Wi-Fi is a standard for Ethernet connection. However, each such wireless interconnect solution can only support the connectivity of a limited set of peripheral devices. For example, the Wi-Fi standard aims to decouple Ethernet cards and the UWB allows the wireless connection of USB devices, such as a mouse, a keyboard, a printer and the like.
It would be therefore highly advantageous to provide a solution that enables the wireless connection between all types of peripheral devices to the computing device.